1. Field of the Invention
The present invention relates to a frequency and phase comparator suitable for use in a phase locked loop circuit and a motor phase controlling circuit.
2. Description of the Prior Art
In recent years, with the advent of digital audio such as satellite broadcast, digital-to-analog converters which process sound signals sampled at different sampling frequencies flood the market. For example, the transfer rate of digital sound of the satellite broadcast is approximately 0.8 megabits per second in A mode stereo and approximately 1.5 megabits per second in B mode stereo. To cope with these different transfer rates, it is necessary to provide a phase locked loop (PLL) circuit which follows the transfer rate of the digital sound signal transmitted to the apparatus. For such a PLL circuit, a phase comparator having only a phase comparing function cannot be used since the pull-in range (locking ability) is small, so that a frequency and phase comparator having a frequency comparing function as well is indispensable.
Conventionally, a circuit as shown in FIG. 1 is generally used as the frequency and phase comparator. In the figure, reference numerals 20 and 21 represent flip-flops, reference numeral 22 represents an inverter, reference numeral 23 represents an AND circuit, reference numeral 26 represents a P-type metal oxide semiconductor field effect transistor (MOSFET), and reference numeral 27 is an N-type MOSFET. Reference numeral 28 represents a power terminal connected to a power source V.sub.DD.
An operation of the conventional frequency and phase comparator thus arranged will be described. The D flip-flop 20 has its one input D terminal pulled up by a supply voltage V.sub.DD through a terminal 28a. To its clock terminal C, a signal F.sub.REF is input. The output from a Q terminal of the flip-flop 20 is input to the inverter 22 through a node A and coupled to one input terminal of the AND terminal 23. The output of the inverter 22 is input to a gate of the P-type MOSFET.
The flip-flop 21 also has its one input D terminal pulled up by the supply voltage V.sub.DD through the terminal 28b, and to its clock terminal C, a signal F.sub.VCO is input. The output from a Q terminal of the flip-flop 21 is coupled to the other input terminal of the AND circuit 23 through a node B and input to a gate of the N-type MOSFET 27. The output of the AND circuit 23 is connected to reset input terminals of the flip-flops 20 and 21. When the voltage level of the nodes A and B are both high, the level of the output of the AND circuit 23 is high, so that the flip-flops 20 and 21 are reset.
Referring to FIG. 2, there are shown signal waveforms of elements of the circuit of FIG. 1. F.sub.REF is the waveform of the input of the flip-flop 20. F.sub.VCO is the waveform of the input of the flip-flop 21. The three waveforms A, B and O therebelow are the waveforms generated at the nodes A, B and O, respectively. In this figure, a period t.sub.1 shows a case where the phase of the waveform F.sub.VCO is delayed from that of the waveform F.sub.REF, a period t.sub.2 shows a case where their phases coincide with each other, and a period t.sub.3 shows a case where the phase of the waveform F.sub.VCO precedes that of the waveform F.sub.REF.
The outputs from the Q terminals of the flip-flops 20 and 21 are used to control the MOSFETs 26 and 27. As the output of the frequency and phase comparator which appears at the node 0, the output of the supply voltage V.sub.DD appears when only the MOSFET 26 is ON, i.e. during the period t.sub.1, and the output of the ground voltage appears when only the MOSFET 27 is ON, i.e. during the period t.sub.3. When the MOSFETs 26 and 27 are both OFF, i.e. during the period t.sub.2 and when there is no input to any of the flip-flops 20 and 21, the output of the frequency and phase comparator is always in a high impedance state.
In the above-described conventional arrangement, however, since the output pulse widths at the nodes A and B are small when the phase difference between the waveforms F.sub.REF and F.sub.VCO is very small, the output pulse may disappear according to the frequency characteristics of the MOSFETs 26 and 27, so that a dead band (a range between M and F) as shown in FIG. 3 is formed in the input-output characteristics.
When such a frequency and phase comparator is used, for example, in a PLL circuit, the PPL circuit not only cannot precisely follow the input frequency but also behaves as if it oscillated in the dead band.